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S3C72I9/P72I9
PRODUCT OVERVIEW
1
OVERVIEW
PRODUCT OVERVIEW
The S3C72I9 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With an up-to-896-dot LCD direct drive capability, 8-bit timer/counter 0, 16-bit timer/counter 1, and serial I/O, the S3C72I9 offers an excellent design solution for a wide variety of applications which require LCD functions. Up to 39 pins of the 100-pin QFP package can be dedicated to I/O. Eight vectored interrupts provide fast response to internal and external events. In addition, the S3C72I9's advanced CMOS technology provides for low power consumption and a wide operating voltage range.
OTP
The S3C72I9 microcontroller is also available in OTP (One Time Programmable) version, S3P72I9. S3P72I9 microcontroller has an on-chip 32 K-byte one-time-programable EPROM instead of masked ROM. The S3P72I9 is comparable to S3C72I9, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C72I9/P72I9
FEATURES SUMMARY
Memory * * 8,192 x 4-bit RAM (excluding LCD display RAM) 32,768 x 8-bit ROM * 39 I/O Pins * * I/O: 35 pins Input only: 4 pins Interrupts * LCD Controller/Driver * * * * 56 segments and 16 common terminals 8 and 16 common selectable Internal resistor circuit for LCD bias All dot can be switched on/off Bit Sequential Carrier * Supports 16-bit serial data transfer in arbitrary format * * Four internal vectored interrupts Four external vectored interrupts Two quasi-interrupts * Watch Timer * Time interval generation: 0.5 s, 3.9 ms at 32.768 Hz 4 frequency outputs to BUZ pin Clock source generation for LCD
8-bit Basic Timer * * 4 interval timer functions Watchdog timer
Power-Down Modes * * * Idle mode (only CPU clock stops) Stop mode (main system clock and CPU clock stop) Sub-system clock stop mode
8-bit Timer/Counter 0 * * * * * Programmable 8-bit timer External event counter Arbitrary clock frequency output External clock signal divider Serial I/O interface clock generator
Oscillation Sources * * * * * Crystal, ceramic, or RC for main system clock Crystal oscillator for subsystem clock Main system clock frequency: 0.4 - 6 MHz Subsystem clock frequency: 32.768 kHz CPU clock divider circuit (by 4, 8, or 64)
16-Bit Timer/Counter 1 * * * * Programmable 16-bit timer External event counter Arbitrary clock frequency output External clock signal divider
Instruction Execution Times * * * 0.67, 1.33, 10.7 s at 6 MHz 0.95, 1.91, 15.3 s at 4.19 MHz 122 s at 32.768 kHz
8-bit Serial I/O Interface * * * * 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable Internal or external clock source
Operating Temperature * - 40 C to 85 C
Operating Voltage Range * 1.8 V to 5.5 V (3.0 MHz @ 1.8 V)
Memory-Mapped I/O Structure * Data memory bank 15 Package Type * 100-pin QFP
1-2
S3C72I9/P72I9
PRODUCT OVERVIEW
BLOCK DIAGRAM
XIN RESET
P1.0-P1.3/ INT0-INT4 P2.0/CLO P2.1/LCDCK P2.2/LCDSY P3.0/TCLO0 P3.1/TCLO1 P3.2/TCL0 P3.3/TCL1 P4.0-P4.3/ COM8-COM11 P5.0-P5.3/ COM12-COM15 P6.0-P6.3 SEG55-SEG52 KS4-KS7 P7.0-P7.3 SEG51-SEG48
XOUT
Basic Timer
Watch Timer
XTIN XTOUT
VLC1-VLC5
Input Port 1 Interrupt Control Block Clock Instruction Register LCD Driver/ Controller
COM0-COM7 P4.0-P5.3/ COM8-COM15 SEG0-SEG39
I/O Port 2
I/O Port 3
Internal Interrupts Serial I/O
P9.3-P6.0/ SEG40-SEG55
I/O Port 4 Instruction I/O Port 5 Arithmetic and Logic Unit Program Status Word
P0.0/SCK/KO P0.1/SO/K1 P0.2/SI/K2 P0.3/BUZ/K3
I/O Port 0 8-Bit Timer/ Counter 0
I/O Port 6 I/O Port 7
Stack Pointer
P8.0-P8.3 SEG47-SEG44 P9.0-P9.3 SEG43-SEG40
I/O Port 8 I/O Port 9
8192 x 4-Bit Data Memory
32 K Byte Program Memory
16-Bit TImer/ Counter 1
Figure 1-1. S3C72I9 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C72I9/P72I9
PIN ASSIGNMENTS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
SEG4 SEG3 SEG2 SEG1 SEG0 VLC5 VLC4 VLC3 VLC2 VLC1 P0.0/SCK/K0 P0.1/SO/K1 P0.2/SI/K2 P0.3/BUZ/K3 VDD VSS XOUT XIN TEST XTIN XTOUT RESET P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/CLO P2.1/LCDCK P2.2/LCDSY P3.0/TCLO0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S3C72I9 (100-QFP-1420C)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 P9.3/SEG40 P9.2/SEG41 P9.1/SEG42 P9.0/SEG43 P8.3/SEG44 P8.2/SEG45 P8.1/SEG46 P8.0/SEG47 P7.3/SEG48 P7.2/SEG49 P7.1/SEG50 P7.0/SEG51 P6.3/SEG52/K7 P6.2/SEG53/K6 P6.1/SEG54/K5
Figure 1-2. S3C72I9 100-QFP Pin Assignment Diagram
1-4
P3.1/TCLO1 P3.2/TCL0 P3.3/TCL1 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 P4.0/COM8 P4.1/COM9 P4.2/COM10 P4.3/COM11 P5.0/COM12 P5.1/COM13 P5.2/COM14 P5.3/COM15 P6.0/SEG55/K4
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
S3C72I9/P72I9
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C72I9 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port. 1-bit and 4-bit read/write and test are possible. Individual pins are software configurable as input or output. Individual pins are software configurable as opendrain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 4-bit input port. 1-bit and 4-bit read and test are possible. 4-bit pull-up resistors are assignable by software. Same as port 0 except that port 2 is 3-bit I/O port. Number 11 12 13 14 Share Pin SCK/K0 SO/K1 SI/K2 BUZ/K3
P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P3.0 P3.1 P3.2 P3.3 P4.0-P4.3 P5.0-P5.3
I
23 24 25 26 27 28 29 30 31 32 33 42-45 46-49
INT0 INT1 INT2 INT4 CLO LCDCK LCDSY TCLO0 TCLO1 TCL0 TCL1 COM8COM11 COM12COM15
I/O
I/O
Same as port 0.
I/O
4-bit I/O ports. 1-, 4-bit or 8-bit read/write and test are possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. Same as P4, P5.
P6.0-P6.3
I/O
50-53
SEG55/K4SEG52/K7 SEG51SEG48 SEG47SEG44 SEG43SEG40 P0.0/K0 P0.1/K1 P0.2/K2 P0.3/K3 P1.0, P1.1
P7.0-P7.3 P8.0-P8.3 P9.0-P9.3 SCK SO SI BUZ INT0, INT1 I/O I/O I/O I/O I Serial I/O interface clock signal. Serial data output. Serial data input. 2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for buzzer signal. External interrupts. The triggering edge for INT0 and INT1 is selectable. I/O Same as P4, P5.
54-57 58-61 62-65 11 12 13 14 23, 24
1-5
PRODUCT OVERVIEW
S3C72I9/P72I9
Table 1-1. S3C72I9 Pin Descriptions (Continued) Pin Name INT2 INT4 CLO LCDCK LCDSY TCLO0 TCLO1 TCL0 TCL1 COM0-COM7 COM8-COM11 COM12-COM15 SEG0-SEG39 SEG40-SEG43 SEG44-SEG47 SEG48-SEG51 SEG52-SEG55 K0-K3 K4-K7 VDD VSS RESET VLC1-VLC5 Xin, Xout XTin, XTout TEST - - I - - - I Main power supply. Ground. Reset signal. LCD power supply. Crystal, Ceramic or RC oscillator pins for system clock. Crystal oscillator pins for subsystem clock. Test signal input. (must be connected to VSS) I/O External interrupt. The triggering edge is selectable. O I/O LCD segment signal output. Pin Type I I I/O I/O I/O I/O I/O I/O I/O O I/O Description Quasi-interrupt with detection of rising or falling edges. External interrupt with detection of rising or falling edges. Clock output . LCD clock output for display expansion. LCD synchronization clock output for display expansion. Timer/counter 0 clock output. Timer/counter 1 clock output. External clock input for timer/counter 0. External clock input for timer/counter 1. LCD common signal output. Number 25 26 27 28 29 30 31 32 33 34-41 42-45 46-49 5-1, 100-66 65-62 61-58 57-54 53-50 11-14 50-53 15 16 22 10-6 18, 17 20, 21 19 Share Pin P1.2 P1.3 P2.0 P2.1 P2.2 P3.0 P3.1 P3.2 P3.3 - P4.0-P4.3 P5.0-P5.3 - P9.3-P9.0 P8.3-P8.0 P7.3-P7.0 P6.3/K7-P6.0/K4 P0.0-P0.3 P6.0-P6.3 - - - - - - -
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
1-6
S3C72I9/P72I9
PRODUCT OVERVIEW
Table 1-2. Overview of S3C72I9 Pin Data Pin Names P0.1, P0.3 P0.0, P0.2 P1.0-P1.3 P2.0-P2.2 P3.0-P3.1 P3.2-P3.3 P4.0-P4.3 P5.0-P5.3 P6.0-P6.3 P7.0-P7.3 P8.0-P8.3 P9.0-P9.3 COM0-COM7 SEG0-SEG39 VDD VSS RESET VLC1-VLC5 XIN, XOUT XTIN, XTOUT TEST Share Pins SO/K1, BUZ/K3 SCK/K0, SI/K2 INT0-INT2, INT4 CLO, LCDCK, LCDSY TCLO0, TCLO1 TCL0, TCL1 COM8-COM11 COM12-COM15 SEG55/K4-SEG52/K7 SEG51-SEG48 SEG47-SEG44 SEG43-SEG40 - - - - - - - - - I/O Type I/O I/O I I/O I/O I/O I/O I/O I/O I/O O O - - I - - - I Reset Value Input Input Input Input Input Input Input Input Input Input High High - - - - - - - Circuit Type E-1 E-2 A-3 E E E-1 H-13 H-16 H-13 H-13 H-3 H-15 - - B - - - -
1-7
PRODUCT OVERVIEW
S3C72I9/P72I9
PIN CIRCUIT DIAGRAMS
VDD
VDD Pull-Up Resistor In
P-Channel In N-Channel
Schmitt Trigger
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
VDD Pull-Up Resistor P-Channel In Pull-Up Resistor Enable Data
VDD
P-Channel Out
Output DIsable Schmitt Trigger
N-Channel
Figure 1-4. Pin Circuit Type A-3
Figure 1-6. Pin Circuit Type C
1-8
S3C72I9/P72I9
PRODUCT OVERVIEW
VDD PNE Pull-up Resistor Pull-up Resistor Enable I/O N-CH
VDD
P-CH Data Output DIsable
Figure 1-7. Pin Circuit Type E
VDD PNE Pull-up Resistor Pull-up Resistor Enable I/O N-CH
VDD
P-CH Data Output DIsable
Schmitt Trigger
Figure 1-8. Pin Circuit Type E-1
1-9
PRODUCT OVERVIEW
S3C72I9/P72I9
VDD PNE Pull-up Resistor Pull-up Resistor Enable I/O N-CH
VDD
P-CH Data Output DIsable
Schmitt Trigger
Figure 1-9. Pin Circuit Type E-2
1-10
S3C72I9/P72I9
PRODUCT OVERVIEW
VDD
VLC1
COM
Out
VLC4
VLC5
Figure 1-10. Pin Circuit Type H-3
VDD
VLC2
SEG
Out
VLC3
VLC5
Figure 1-11. Pin Circuit Type H-15
1-11
PRODUCT OVERVIEW
S3C72I9/P72I9
VDD Pull-up Resistor Pull-up Resistor Enable COM/SEG Output Disable Data Type H-3 P-CH
Type C
I/O
Figure 1-12. Pin Circuit Type H-13
VDD Pull-up Resistor Pull-up Resistor Enable SEG Output Disable Data Type H-15 P-CH
Type C
I/O
Schmitt Trigger
Figure 1-13. Pin Circuit Type H-16
1-12
S3C72I9/P72I9
ELECTRICAL DATA
14
OVERVIEW
ELECTRICAL DATA
In this section, information on S3C72I9 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- Main system clock oscillator characteristics -- Subsystem clock oscillator characteristics -- I/O capacitance -- A.C. electrical characteristics -- Operating voltage range Miscellaneous Timing Waveforms -- A.C timing measurement point -- Clock timing measurement at XIN -- Clock timing measurement at XTIN -- TCL timing -- Input timing for RESET -- Input timing for external interrupts -- Serial data transfer timing Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request
14-1
ELECTRICAL DATA
S3C72I9/P72I9
Table 14-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO I OH I OL Ports 0-9 - One I/O pin active All I/O pins active Output Current Low One I/O pin active Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 35 + 30 (Peak value) + 15 (note) Total for ports 0, 2-9 Operating Temperature Storage Temperature TA Tstg - - + 100 (Peak value) + 60 (note) - 40 to + 85 - 65 to + 150
Duty . C C
Units V V V mA
mA
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value x
Table 14-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Output High Voltage Output Low Voltage VOH Conditions All input pins except those specified below for VIH2-VIH3 Ports 0, 1, 6, P3.2, P3.3, and RESET XIN, XOUT, and XTIN All input pins except those specified below for VIL2-VIL3 Ports 0, 1, 6, P3.2, P3.3, and RESET XIN, XOUT, and XTIN VDD = 4.5 V to 5.5 V IOH = - 1 mA Ports 0, 2-9 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 0, 2-9 VDD - 1.0 - Min 0.7 VDD 0.8 VDD VDD - 0.1 - - Typ - Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 - V V Units V
VOL
-
-
2.0
V
14-2
S3C72I9/P72I9
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Leakage Current Symbol ILIH1 Conditions VI = VDD All input pins except those specified below for ILIH2 VI = VDD XIN, XOUT, XTIN, and RESET VI = 0 V All input pins except those specified below for ILIH2 VI = 0 V XIN, XOUT, and XTIN VO = VDD All output pins VO = 0 V All output pins VI = 0 V; VDD = 5 V Port 0-9 VDD = 3 V RL2 VI = 0 V; VDD = 5 V, RESET VDD = 3 V LCD Voltage Dividing Resistor |VDD-COMi| Voltage Drop (i = 0-15) |VDD-SEGx| Voltage Drop (x = 0-55) VLC1 Output Voltage VLC2 Output Voltage VLC3 Output Voltage VLC4 Output Voltage RLCD TA = 25 C - - - - -3 A Min - Typ - Max 3 Units A
ILIH2 Input Low Leakage Current Output High Leakage Current Output Low Leakage Current Pull-Up Resistor ILIL1
20
ILIL2 ILOH
- 20 3 A
ILOL
-
-
-3
A
RLI
25 50 100 200 25
47 95 220 450 55
100 200 400 800 80
k
k
VDC
- 15 A per common pin
-
-
120
mV
VDS
- 15 A per segment pin
-
-
120
VLC1 VLC2 VLC3 VLC4
LCD clock = 0 Hz, VLC5 = 0 V
0.8 VDD - 0.2 0.6 VDD - 0.2 0.4 VDD - 0.2 0.2 VDD - 0.2
0.8 VDD 0.6 VDD 0.4 VDD 0.2 VDD
0.8 VDD + 0.2 0.6 VDD+ 0.2 0.4 VDD + 0.2 0.2 VDD + 0.2
V
14-3
ELECTRICAL DATA
S3C72I9/P72I9
Table 14-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current Symbol IDD1 (2) Conditions VDD = 5 V 10% Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% IDD2 (2) Idle mode; VDD = 5 V 10% Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% IDD3 (3) IDD4 (3) IDD5 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz Min - Typ 5.1 3.9 2.5 1.8 1.3 1.2 Max 10.0 7.5 4.0 3.0 2.5 1.8 Units mA
6.0 MHz 4.19 MHz -
0.5 0.44 22.8 6.4 2.5 0.5 0.2 0.1
1.5 1.0 35 15 5 3 3 2 A
VDD = 3 V 10% 32 kHz crystal oscillator Idle mode; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% SCMOD = 0000B XT = 0V SCMOD = 0100B
NOTES: 1. Data includes power consumption for subsystem clock oscillation. 2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. 3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, output port drive currents.
14-4
S3C72I9/P72I9
ELECTRICAL DATA
Table 14-3. Main System Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration
XIN XOUT
Parameter Oscillation frequency (1)
Test Condition -
Min 0.4
Typ -
Max 6.0
Units MHz
C1
C2
Stabilization time (2)
Stabilization occurs when VDD is equal to the minimum oscillator voltage range; VDD = 3.0 V. -
-
-
4
ms
Crystal Oscillator
XIN
XOUT
Oscillation frequency (1)
0.4
-
6.0
MHz
C1
C2
Stabilization time (2)
VDD = 3.0 V VDD = 2.0 V to 5.5 V
- - 0.4
- - -
10 30 6.0
ms
External Clock
XIN
XOUT
XIN input frequency (1)
-
MHz
XIN input high and low level width (tXH, tXL) RC Oscillator
XIN R XOUT
- R = 20 k, VDD = 5 V
83.3 -
- 2
1250 -
ns MHz
Frequency
R = 39 k, VDD = 3 V
-
1
-
NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated.
14-5
ELECTRICAL DATA
S3C72I9/P72I9
Table 14-4. Recommended Oscillator Constants (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Manufacturer Series Number (1) FCR FCR CCR M5 MC5 MC3 Frequency Range Load Cap (pF) C1 TDK 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 33
(2)
Oscillator Voltage Range (V) MIN 2.0 2.0 2.0 MAX 5.5 5.5 5.5
Remarks
C2 33
(2)
Leaded Type On-chip C Leaded Type On-chip C SMD Type
(3)
(3)
NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in.
14-6
S3C72I9/P72I9
ELECTRICAL DATA
Table 14-5. Subsystem Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration
XTIN XTOUT
Parameter Oscillation frequency (1)
Test Condition -
Min 32
Typ 32.768
Max 35
Units kHz
C1
C2
Stabilization time (2)
VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V
- - 32
1.0 - -
2 10 100
s
External Clock
XTIN XTOUT
XTIN input frequency (1)
-
kHz
XTIN input high and low level width (tXTL, tXTH)
-
5
-
15
s
NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 14-6. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF
14-7
ELECTRICAL DATA
S3C72I9/P72I9
Table 14-7. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time (note) Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V TCL0, TCL1 Input Frequency f TI0, f TI1 VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V TCL0, TCL1 Input High, Low Width tTIH0, tTIL0 tTIH1, tTIL1 tKCY VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V SCK Cycle Time VDD = 2.7 V to 5.5 V; Input Internal SCK source; Output VDD = 2.0 V to 5.5 V; Input Internal SCK source; Output SCK High, Low Width tKH, tKL VDD = 2.7 V to 5.5 V; Input Internal SCK source; Output VDD = 2.0 V to 5.5 V; Input Internal SCK source; Output SI Setup Time to SCK High tSIK VDD = 2.7 V to 5.5 V; Input VDD = 2.7 V to 5.5 V; Output VDD = 2.0 V to 5.5 V; Input VDD = 2.0 V to 5.5 V; Output SI Hold Time to SCK High tKSI VDD = 2.7 V to 5.5 V; Input VDD = 2.7 V to 5.5 V; Output VDD = 2.0 V to 5.5 V; Input VDD = 2.0 V to 5.5 V; Output 0.48 1.8 800 650 3200 3800 325 tKCY/250 1600 tKCY/2150 100 150 150 500 400 400 600 500 - - ns - - ns - - ns - - ns - Min 0.67 0.95 0 - Typ - Max 64 64 1.5 1 - s MHz Units s
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
14-8
S3C72I9/P72I9
ELECTRICAL DATA
Table 14-7. A.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Output Delay for SCK to SO Symbol tKSO Conditions VDD = 2.7 V to 5.5 V; Input VDD = 2.7 V to 5.5 V; Output VDD = 2.0 V to 5.5 V; Input VDD = 2.0 V to 5.5 V; Output Interrupt Input High, Low Width RESET Input Low Width tINTH, tINTL tRSL INT0, INT1, INT2, INT4, K0-K7 Input 10 10 - - Min - Typ - Max 300 250 1000 1000 - - s s Units ns
NOTE: Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
CPU Clock 1.5 MHz
Main Oscillator Frequency (Divided by 4) 6 MHz
1.05 MHz 750 kHz
4.2 MHz 3 MHz
15.6 kHz 1 2 1.8 V Supply Voltage (V) CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64) 3 4 5 6 7
Figure 14-1. Standard Operating Voltage Range
14-9
ELECTRICAL DATA
S3C72I9/P72I9
Table 14-8. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 1.8 V - Released by RESET Released by interrupt Min 1.8 - 0 - - Typ - 0.1 - 217/fx
(2)
Max 5.5 10 - - -
Unit V A s ms
NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
14-10
S3C72I9/P72I9
ELECTRICAL DATA
TIMING WAVEFORMS
Internal RESET Operation Stop Mode Data Retention Mode Idle Mode Normal Mode
~ ~ ~ ~
VDD
VDDDR Execution of STOP Instrction RESET tWAIT tSREL
Figure 14-2. Stop Mode Release Timing When Initiated by RESET
Idle Mode
~ ~ ~ ~
Stop Mode Data Retention Mode
Normal Mode
VDD
VDDDR Execution of STOP Instrction
tSREL
tWAIT Power-down Mode Terminating Signal (Interrupt Request)
Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request
14-11
ELECTRICAL DATA
S3C72I9/P72I9
0.8 VDD Measurement Points 0.2 VDD
0.8 VDD
0.2 VDD
Figure 14-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx tXL tXH
XIN
VDD - 0.1 V 0.1 V
Figure 14-5. Clock Timing Measurement at XIN
1/fxt tXTL tXTH
XTIN
VDD - 0.1 V 0.1 V
Figure 14-6. Clock Timing Measurement at XTIN
14-12
S3C72I9/P72I9
ELECTRICAL DATA
1/fTI tTIL tTIH
TCL0
0.8 VDD 0.2 VDD
Figure 14-7. TCL Timing
tRSL
RESET 0.2 VDD
Figure 14-8. Input Timing for RESET Signal
tINTL
tINTH
INT0, 1, 2, 4, K0 to K7
0.8 VDD 0.2 VDD
Figure 14-9. Input Timing for External Interrupts and Quasi-Interrupts
14-13
ELECTRICAL DATA
S3C72I9/P72I9
tKCY tKL SCK 0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD SI Input Data 0.2 VDD tKSO tKH
SO
Output Data
Figure 14-10. Serial Data Transfer Timing
14-14
S3C72I9/P72I9
MICHANICAL DATA
15
OVERVIEW
MICHANICAL DATA
The S3C72I9 microcontrollers are available in a 100-QFP-1420C package.
23.90 0.3 0-8 20.00 0.2 0.15
+0.10 -0.05
17.90 0.3
14.00 0.2
100-QFP-1420C
0.80 0.20
0.10 MAX
#100 (0.83) 0.3 0.1 0.10 MAX 0.65 (0.58)
#1
0.05 MIN 2.65 0.10 3.00 MAX
0.80 0.20 NOTE: Dimensions are in millimeters.
Figure 15-1. 100-QFP Package Dimension
15-1
S3C72I9/P72I9
S3P72I9 OTP
16
OVERVIEW
S3P72I9 OTP
The S3P72I9 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72I9 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P72I9 is fully compatible with the S3C72I9, both in function and in pin configuration. Because of its simple programming requirements, the S3P72I9 is ideal for use as an evaluation chip for the S3C72I9.
16-1
S3P72I9 OTP
S3C72I9/P72I9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
SEG4 SEG3 SEG2 SEG1 SEG0 VLC5 VLC4 VLC3 VLC2 VLC1 P0.0/SCK/K0 P0.1/SO/K1 SDAT/P0.2/SI/K2 SCLK/P0.3/BUZ/K3 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET RESET P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/CLO P2.1/LCDCK P2.2/LCDSY P3.0/TCLO0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S3P72I9 (100-QFP-1420C)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 P9.3/SEG40 P9.2/SEG41 P9.1/SEG42 P9.0/SEG43 P8.3/SEG44 P8.2/SEG45 P8.1/SEG46 P8.0/SEG47 P7.3/SEG48 P7.2/SEG49 P7.1/SEG50 P7.0/SEG51 P6.3/SEG52/K7 P6.2/SEG53/K6 P6.1/SEG54/K5
Figure 16-1. S3P72I9 Pin Assignments (100-QFP Package)
16-2
P3.1/TCLO1 P3.2/TCL0 P3.3/TCL1 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 P4.0/COM8 P4.1/COM9 P4.2/COM10 P4.3/COM11 P5.0/COM12 P5.1/COM13 P5.2/COM14 P5.3/COM15 P6.0/SEG55/K4 NOTE: The bolds indicate an OTP pin name.
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
S3C72I9/P72I9
S3P72I9 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P0.2 Pin Name SDAT Pin No. 13 During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to + 5 V during programming.
P0.3 TEST
SCLK VPP (TEST)
14 19
I/O I
RESET VDD/VSS
RESET VDD/VSS
22 15/16
I I
Table 16-2. Comparison of S3P72I9 and S3C72I9 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 1.8 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5 V 100 QFP User Program 1 time 100 QFP Programmed at the factory S3P72I9 32 Kbyte EPROM S3C72I9 32 Kbyte mask ROM 1.8 V to 5.5 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P72I9, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 16-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/ MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode
NOTE: "0" means Low level; "1" means High level.
16-3
S3P72I9 OTP
S3C72I9/P72I9
Table 16-4. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current Symbol IDD1 (2) Conditions VDD = 5 V 10% Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% IDD2 (2) Idle mode; VDD = 5 V 10% Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% IDD3 (3) IDD4 (3) IDD5 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz Min - Typ 5.1 3.9 2.5 1.8 1.3 1.2 Max 10.0 7.5 4.0 3.0 2.5 1.8 Units mA
6.0 MHz 4.19 MHz -
0.5 0.44 22.8 6.4 2.5 0.5 0.2 0.1
1.5 1.0 35 15 5 3 3 2 A
VDD = 3 V 10% 32 kHz crystal oscillator Idle mode; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% Stop mode; VDD = 5 V 10% Stop mode; VDD = 3 V 10% SCMOD = 0000B XT = 0V SCMOD = 0100B
NOTES: 1. Data includes power consumption for subsystem clock oscillation. 2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. 3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, output port drive currents.
16-4
S3C72I9/P72I9
S3P72I9 OTP
CPU Clock 1.5 MHz
Main Oscillator Frequency (Divided by 4) 6 MHz
1.05 MHz 750 kHz
4.2 MHz 3 MHz
15.6 kHz 1 2 1.8 V Supply Voltage (V) CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64) 3 4 5 6 7
Figure 16-2. Standard Operating Voltage Range
16-5

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